The present invention relates to the switching of high frequency signals, and more particularly to bussing high frequency crosspoint switches to increase the number of inputs that may be switched to any one output while reducing parasitic reactances that load an output bus.
Outputs of crosspoint switch integrated circuits (ICs) are usually connected together, or bussed, to increase the number of inputs that may be switched to any one output bus, as shown in U.S. Pat. Nos. 5,331,206 and 5,870,028. Of the crosspoint IC outputs bussed together on a given bus, at most the output from one IC is activated at any given time, with those outputs which share the same bus on all other ICs being deactivated. This works fine at low data rates. As the data rate increases, parasitic reactances in the crosspoint switch and on the circuit board or hybrid load the output bus and cause data pulse degradation.
Several methods have been tried to reduce this data pulse degradation problem, such as lowering the impedance of the transmission line to reduce the degradation. The degradation is reduced, but power dissipation is increased with this method. Other methods involve xe2x80x9cbufferingxe2x80x9d of the parasitic reactances with resistors. Again the degradation is reduced and power dissipation suffers. Also buffering with resistors reduces the output amplitude and may shift the output direct current (DC) voltage.
IC input and/or output parasitic reactances may be used to advantage. By adding a second IC pad, a second bond wire with mutual inductance with the first bond wire may be used to decrease the effective IC capacitance. One skilled in the art may optimize this configuration to improve either bandwidth, group delay or port reflections as required by the application. When used on individual inputs or outputs, this circuit is commonly called a xe2x80x9cT-coil.xe2x80x9d This circuit technique may be extended to interconnect multiple crosspoint switch ICs. The drawback of this technique is that it requires twice as many IC pads for each input and output. This substantially raises the area sensitive cost of the IC, especially on ICs where the die area is xe2x80x9cpad limitedxe2x80x9d, i.e., the lower bound for area depends primarily on the number of pads.
At the highest data rates, above 1 Gbit/s to HDTV or SONET OC-48 data rates, the bus looks like a transmission line and connections to the ICs look like transmission line stubs. These stubs cause reflections and decrease the bandwidth of the transmission lines. Reflections and decreased bandwidth increase jitter, which in some cases makes data recovery impossible.
What is desired is a technique for bussing high frequency crosspoint switches that decreases parasitic reactances without increasing area cost on ICs.
Accordingly the present invention provides a technique for bussing high frequency crosspoint switches by having two output ports for each crosspoint IC coupled to an exterior portion of an output transmission line bus. The output transmission line bus runs from outside the IC, extending into the IC package close to the edge of the die. A bond wire connects the internal portion of the output transmission line bus to an output pad on the IC die which has a parasitic capacitance. This eliminates stub terminations on the output transmission line bus while compensating for the parasitic capacitance.
The objects, advantages and other novel features of the present invention are apparent from the following detailed discussion when read in conjunction with the appended claims and attached drawing.